1. The Field of the Invention
The present invention relates to electrical insulators for active elements such as transistors, capacitors, resistors, and diodes. In particular, the present invention relates to such active elements and methods of improving the performance thereof by reducing parasitic effects of capacitance therein by electrical insulation structures and techniques for making the same.
2. The Relevant Technology
Integrated circuits provide the logic and memory of computers and other intelligent electronic products. Electronic xe2x80x9cchipsxe2x80x9d on which the integrated circuits are situated have advanced in capability to a level that has made computers and other intelligent electronic devices highly functional. Integrated circuits are also being manufactured economically, allowing the highly functional computers and other intelligent electronic products to be provided to consumers at an affordable cost.
Integrated circuits are currently manufactured by an elaborate process in which semiconductor devices, insulating films, and patterned conducting films are sequentially constructed in a predetermined arrangement on a semiconductor substrate. In the context of this document, the term xe2x80x9csemiconductor substratexe2x80x9d is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term xe2x80x9csubstratexe2x80x9drefers to any supporting structure including but not limited to the semiconductor substrates described above.
Conventional semiconductor devices which are formed on a semiconductor substrate include capacitors, resistors, transistors, diodes, and the like. In advanced manufacturing of integrated circuits, hundreds of thousands of these semiconductor devices are formed on a single semiconductor substrate.
The computer and electronics industry is constantly under market demand to increase the speed at which integrated circuits operate, to increase the capabilities of integrated circuits, and to reduce the cost of integrated circuits. One manner of accomplishing this task is to increase the density with which the semiconductor devices can be formed on a given surface area of a single semiconductor substrate. In so doing, the semiconductor devices must be decreased in dimension in a process known as miniaturization. In order to meet market demands and further the miniaturization of integrated circuits, the processes by which the semiconductor devices are formed are in need of improvement. The challenge in miniaturizing integrated circuits is to do so without greatly increasing the cost of the processes by which integrated circuits are manufactured. Accordingly, the new processes must also be relatively simple and cost effective.
One structure which is frequently formed in integrated circuit manufacturing and for which improved methods of formation are needed is the MOS transistor. The MOS transistor has source/drain regions and a gate.
MOS transistor performance is a contemporary concern. Relating to performance are the criteria of how much drive capability the transistor has and how much current can drive through the transistor. The capacitance of a transistor slows down the transistor and may slow down a circuit of which the transistor forms a part. The capacitance loading of a transistor is the charge that needs to accumulate in the transistor before the transistor conducts charge in the channel between source/drain regions.
Fringing capacitance is part of the gate-to-source/drain capacitance and is dependent upon the thickness of a spacer surrounding the gate of the transistor, where the spacer extends from a lateral side of the gate to the source/drain regions, and upon the ion implanted doping profile of the source/drain regions. Fringing capacitance has a parasitic effect on the transistor. It is desirable to reduce the fringing capacitance because fringing capacitance adds loading to the logic gates.
In conventional MOS transistor fabrication flow, a layer of conductive material, such as polysilicon, is deposited upon a relatively thin gate oxide layer and is patterned and etched to form a transistor gate. Following this, a reoxidation step of the gate is performed to grow a thermal oxide so as to smooth corners around the gate. The reoxidation step also increases the oxide thickness near the gate as well as at a selected location where the source/drain regions are to be formed, while reducing the peak electric field in the underlying substrate in those regions. Consequently, hot-carrier effects will be suppressed. A low/medium dose ion doping implant is performed. A layer material is then deposited, typically an oxide or a nitride, which is then subjected to a spacer etch to form a spacer around sidewalls of the gate. The spacer is typically about 1000 xc3x85 thick. In this sequence of processing, the spacer dielectric is in direct contact with the gate sidewall. Heavy dose source/drain implants follow to form the source/drain regions proximal to the spacer.
Attempts have been made to reduce transistor fringing capacitance in MOS transistor. Where the MOS transistor has a spacer extending from a lateral side of the gate to the source/drain regions, fringing capacitance is determined by the relative dielectric constant of the spacer material. Typically, the spacer is composed of a material having a low dielectric constant of about 2.3. Silicon dioxide or silicon nitride can be used to form the spacer, which have dielectric constants of about 3.5 and about 7.5, respectively. In contrast, air and a vacuum have dielectric constants of about 1.1 and 1.0 respectively. It would be desirable to lower the dielectric constant of the spacer material to reduce the fringing capacitance.
Other attempts have been made to reduce the fringing capacitance by minimizing the size of the spacer surrounding the gate of the transistor, either alone or in combination with reducing the distance that the source/drain regions protrude underneath the gate. Such reductions, however, may yield a spacer having less structural integrity.
What is needed are methods and structures to increase MOS transistor performance, drive current and capacity by reducing the loading and fringing capacitance thereof without reducing spacer structural integrity.
In accordance with the invention as embodied and broadly described herein, it is an application thereof to reduce fringe capacitance in active elements of integrated circuits, including by way of example and not limitation, transistors, diodes, capacitors, and resistors. To accomplish a device and method of making the same which overcomes the foregoing prior art problems and disadvantages, there is provided an electrically insulated structure having a semiconductor substrate with a raised feature projecting therefrom. A void is formed between the raised feature and a cover layer. The void is preferably substantially closed off the ambient by a cap formed over an opening thereto. The cap can be situated over the opening so as to close the void, and can be upon both the raised feature and the cover layer. The void can be used as an electrical insulator when formed between and adjacent to electrically conductive regions, such as the gate and source/drain regions of a transistor. The void can also act as an insulator when situated between the components of capacitors, resistors, and diodes. The void is a preferred insulator in that, when filled with air, the void has a dielectric constant of about one (1).
A method for producing the electrically insulated structure is provided by forming a raised feature projecting from a semiconductor substrate, forming a layer of a primary material over the raised feature, and forming a layer of a secondary material over the layer of the primary material. Next, a recess is formed in the primary material and situated between the layer of the secondary material and the raised feature. There is then formed a cover layer over an opening to the recess so as to form a void.
To form the recess described above, a selective removal process, such as an etch, can be used. The selective removal process removes the primary material situated in between the raised feature and the secondary material at a faster material removal rate than the material removal rate of either the secondary material or the material of the raised feature. In the case of an etch, a wet etch, dry etch, or combined wet and dry etch processes can be performed.
A masking step can be formed performed to form the recess described above, where the mask protects the secondary material, but leaves exposed to a selective removal process the primary material situated in between the raised feature and the secondary material. The selective removal process then removes the primary material situated in between the raised feature and the secondary material at a faster material removal rate than the material removal rate of either the secondary material or the material of the raised feature.
The void can be used to electrically isolate electrically conductive features. For example, the void can be confined between a spacer and a side wall of a gate of a MOS transistor. Alternatively, the void can be formed within a shallow trench situated within a semiconductor substrate and in between and isolating electrically active regions within the semiconductor substrate, such as between diodes.
Additional advantages of the invention will be set forth in the description which follows, and in part will be obvious to those skilled in the art after referring to the following description, or may be learned by the practice of the invention. The advantages of the invention may be realized and obtained by means of the combinations particularly pointed out in the appended claims.